[TriEmbed] Power FETs Vol 25, Issue 27

[Shane Trent]

Brian,

That is correct. You can also make the pull-down larger if you are driving
the pin both directions. In that case the pull-down is more of a protection
to ensure the FET does not turn on at start up or from picking up stray
charge.

Shane

On Thu, Jun 18, 2015 at 5:12 PM, Grawburg <grawburg at myglnc.com> wrote:

> So, if I use a 220 ohm GPIO-Gate resistor and a 100k pull-down I should
> have about 3.3 V to the gate.
>
>
> Brian
>
> ------------------------------
>
> Cc: "TriEmbed Discussion" <triembed at triembed.org>
> Date: 06/18/15 04:25 PM
> Subject: Re: Re[2]: [TriEmbed] Power FETs Vol 25, Issue 27
>
> Brian,
>
> I think we may have figured out why your 33k gate resistor did not work.
> You want a very weak (high resistance) pull-down on the gate to ensure the
> FET turns off when you remove the drive signal (and at power up). A 10k
> pull-down would turn the FET off quickly but would require a much stronger
> signal to turn the FET on. Without any pull-down resistor, enough charge
> could accumulate on the gate to randomly turn on the FET or it could take a
> long time, from seconds to minutes, for the FET to turn off once you remove
> the drive signal.
>
> As, someone mentioned earlier on this thread, the pull-down resistor and
> the I/O pin resistor form a voltage divider. So if you have a 10k pull-down
> and a 33k I/O resistor between the pin and the gate, then the max voltage
> on gate is 10k/(10k +33k) * Vout. So for a 3.3V logic output your gate
> voltage would have been around 0.77V so the FET would not have been close
> to turning on. With a 3.3k I/O resistor the voltage would have been around
> 2.5V, which is still not enough to cause the FET to conduct very well.
>
>


-- 
A blog about some of my projects.  http://fettricks.blogspot.com/
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