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<span dir="ltr" style="margin-top:0; margin-bottom:0;">(this time to all, with update)</span>
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<br><span dir="ltr" style="margin-top:0; margin-bottom:0;">I just found out that running one m33f core and one RISCV core is an option.</span>
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<br><span dir="ltr" style="margin-top:0; margin-bottom:0;">Eben Upton: "They're selectable at boot time: Each port into the bus fabric can be connected either to an M33 or a Hazard3 via a mux. You can even, if you're feeling obtuse, run with one of each."</span>
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<br><span dir="ltr" style="margin-top:0; margin-bottom:0;">Source: https://www.theregister.com/2024/08/08/pi_pico_2_risc_v/</span>
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<br><span dir="ltr" style="margin-top:0; margin-bottom:0;">Pete</span>
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<p>Aug 8, 2024 1:13:58 PM Mike Lisanke <mikelisanke@gmail.com>:</p>
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Any idea Why they made the RISC-V cores Selectable from sw to switch with the ARM cores? Why not enable both? Conflicts?
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It's very interesting that an Open Source core now has potential to create RPi products.
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On Thu, Aug 8, 2024 at 1:09 PM Pete Soper via TriEmbed <<a href="mailto:triembed@triembed.org">triembed@triembed.org</a>> wrote:
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<span dir="ltr" style="margin-top:0px;margin-bottom:0px;"><a href="https://www.raspberrypi.com/products/rp2350/" target="_blank">https://www.raspberrypi.com/products/rp2350/</a></span>
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<br><span dir="ltr" style="margin-top:0px;margin-bottom:0px;">Pete</span>
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Best regards, Mike
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